View PCF5271_4842717.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? freescale semiconductor, inc., 2004. all rights reserved. freescale semiconductor hardware specification mcf5271ec rev. 1.2, 12/2004 technical data table of contents the mcf5271 family is a highly integrated implementation of the coldfire ? family of reduced instruction set computing (r isc) microprocessors. this document describes pertinent features and functions of the mcf5271 family. the mc f5271 family includes the mcf5271 and mcf5270 mi croprocessors. the differences between these part s are summarized below in table 1 . this document is written from the perspective of the mcf5271 and unless otherwise noted, the information applies also to the mcf5270. the mcf5271 family combin es low cost with high integration on the popular version 2 coldfire core with over 96 (dhrystone 2.1) mips at 100mhz. positioned for applications requiring a cost-sensitive 32-bit solution, the mcf5271 family features a 10/100 ethernet mac and optional hardware encryption to ensure the application can be connected and protected. in addition, the mcf5271 family features an enhanced multiply accumulate unit (emac), large on-chip memory (64 kbytes sram, 8 kbytes c onfigurable cache), and a 32-bit sdr sdram memory controller. 1 mcf5271 family configurations ..................... 2 2 block diagram ................................................. 2 3 features .......................................................... 4 4 signal descriptions........................................ 12 5 modes of operation....................................... 16 6 design recommendations ............................ 19 7 mechanicals/pinouts and part numbers ....... 27 8 preliminary electrical characteristics............ 32 9 documentation .............................................. 55 mcf5271 integrated microprocessor hardware specification 32-bit embedded controller division
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 mcf5271 family configurations freescale semiconductor 2 1 mcf5271 family configurations 2 block diagram the superset device in the mcf5271 family comes in a 196 mold array plastic ball grid array (mapbga) package. figure 1 shows a top-level block diagram of the mcf5271. table 1. mcf5271 family configurations module 5270 5271 coldfire v2 core with emac and hardware divide xx system clock 100 mhz performance (dhrystone/2.1 mips) 96 instruction/data cache 8 kbytes static ram (sram) 64 kbytes interrupt controllers (intc) 22 edge port module (eport) xx external interface module (eim) xx 4-channel direct-memory access (dma) xx sdram controller xx fast ethernet controller (fec) xx hardware encryption ?x watchdog timer (wdt) xx four periodic interrupt timers (pit) xx 32-bit dma timers 44 qspi xx uart(s) 33 i 2 c xx general purpose i/o module (gpio) xx jtag - ieee 1149.1 test access port xx package 160 qfp, 196 mapbga 160 qfp, 196 mapbga
block diagram mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 3 figure 1. mcf5271 block diagram 64 kbytes sram (8kx16)x4 eim ethernet v2 coldfire cpu intc0 watchdog pit0 jtag tap cache (1kx32)x2 pit1 pit2 pit3 4 ch dma uart 0 uart 1 i 2 c qspi dtim 0 dtim 1 dtim 2 dtim 3 timer padi ? pin muxing pll clkgen uart 2 8 kbytes edge port sdramc chip ebi selects (to/from padi) (to/from fast controller (fec) fec t n in t n out u n rxd u n txd i2c_sda i2c_scl sdramc qspi u n rts u n cts ports cim (gpio) d[31:0] a[23:0] r/ w cs [3:0] ta tsiz [1:0] tea bs [3:0] div emac dreq[2:0] intc1 arbiter (to/from sram backdoor) (to/from arbiter) skha rnga mdha (to/from padi) cryptography modules dack[2:0] bdm (to/from intc) mux padi) jtag_en
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 features freescale semiconductor 4 3features this document contains information on a new product. specifi cations and informati on herein are subject to change without notice. 3.1 feature overview ? version 2 coldfire variable -length risc processor core ? static operation ? 32-bit address and data path on-chip ? processor core runs at twice the bus frequency ? sixteen general-purpose 32-bit data and address registers ? implements the coldfire instruction set archit ecture, isa_a, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing ? enhanced multiply-accumulate (emac) unit wi th four 48-bit accumulators to support 32-bit signal processing algorithms ? illegal instruction decode that allows for 68k emulation support ? system debug support ? real time trace for determ ining dynamic execution path ? background debug mode (bdm) for in-circuit debugging ? real time debug support, with tw o user-visible hardware breakpoi nt registers (pc and address with optional data) that can be confi gured into a 1- or 2-level trigger ? on-chip memories ? 8-kbyte cache, configurable as instruct ion-only, data-only, or split i-/d-cache ? 64-kbyte dual-ported sram on cpu internal bus, accessible by core and non-core bus masters (e.g., dma, fec) ? fast ethernet controller (fec) ? 10 baset capability, half duplex or full duplex ? 100 baset capability, half duplex or full duplex ? on-chip transmit and receive fifos ? built-in dedicated dma controller ? memory-based flexible descriptor rings ? media independent interface (mii ) to external transceiver (phy) ? three universal asynchronous receiver transmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic ? maskable interrupts ? dma support
features mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 5 ? data formats can be 5, 6, 7 or 8 bits with even, odd or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (urts ) and clear-to-send (ucts ) lines for two uarts ? transmit and receive fifo buffers ?i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master or slave modes support multiple masters ? automatic interrupt genera tion with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to four chip selects available ? master mode operation only ? programmable master bit rates ? up to 16 pre-programmed transfers ? four 32-bit dma timers ? 20-ns resolution at 50 mhz ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input-capture capability with progr ammable trigger edge on input pin ? output-compare with programma ble mode for the output pin ? free run and restart modes ? maskable interrupts on input cap ture or reference-compare ? dma trigger capability on input capture or reference-compare ? four periodic interr upt timers (pits) ? 16-bit counter ? selectable as free running or count down ? software watchdog timer ? 16-bit counter ? low power mode support ? frequency modulated ph ase locked loop (pll) ? crystal or external oscillator reference ? 8 to 25 mhz reference frequency for normal pll mode
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 features freescale semiconductor 6 ? 24 to 50 mhz oscillator refe rence frequency for 1:1 mode ? separate clock output pin ? interrupt controllers (x2) ? support for up to 41 interrupt sources orga nized as follows: 34 fully-programmable interrupt sources and 7 fixed-le vel external interrupt sources ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt sour ce or all interrupt s ources (global mask-all) ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from lo w power modes ? dma controller ? four fully programmable channels ? dual-address and single-address transfer support with 8-, 16- a nd 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers ? source/destination address pointers that can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers supporte d for efficient block movement ? bursting and cycle steal support ? software-programmable connections between the 12 dma requesters in the uarts (3), 32-bit timers (4), plus external logi c (4), and the four dma channels (4) ? external bus interface ? glueless connections to external memory devices (e.g., sram, flash, rom, etc.) ? sdram controller supports 8-, 16- , and 32-bit wide memory devices ? support for n-1-1-1 burst fetc hes from page mode flash ? glueless interface to sram devices with or without byte strobe inputs ? programmable wait state generator ? 32-bit bidirectional data bus ? 24-bit address bus ? up to eight chip selects available ? byte/write enables (byte strobes) ? ability to boot from external memo ries that are 8, 16, or 32 bits wide ? chip configuration module (ccm) ? system configuration during reset ? selects one of four clock modes ? sets boot device and its data port width ? configures output pad drive strength ? unique part identification num ber and part revision number
features mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 7 ?reset ? separate reset in and reset out signals ? six sources of reset: powe r-on reset (por), external, software, watchdog, pll loss of clock, pll loss of lock ? status flag indication of source of last reset ? general purpose i/o interface ? up to 61 bits of general purpose i/o ? bit manipulation supporte d via set/clear functions ? unused peripheral pins may be used as extra gpio ? jtag support for system level board testing 3.2 v2 core overview the processor core is comprised of two separate pipelines th at are decoupled by an instruction buffer. the two-stage instruction fetch pipeline (ifp) is responsib le for instruction-address generation and instruction fetch. the instruction buffer is a first-in-first-out (fif o) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (oep). th e oep includes two pipeline stages. the first stage decodes instructions and selects operands (dsoc) ; the second stage (agex) performs instruction execution and calculates operand ef fective addresses, if needed. the v2 core implements the coldfire instruction set architecture revision a with added support for a separate user stack pointer register and four new instru ctions to assist in bit processing. additionally, the mcf5271 core includes the enhanced multiply-accumulate unit (emac) for improved signal processing capabilities. the emac implements a 4-stage execu tion pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumu lators. supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands as well as a complete set of instructions to process these data types. the emac provides superb support for executi on of dsp operations within the context of a single processor at a minimal hardware cost. 3.3 debug module the coldfire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator deve lopment tools. through a standard debug interface, users can access real-time trace and debug information. this allows the processor and syst em to be debugged at full speed without the need for costly in-circuit emulators. th e debug interface is a supers et of the bdm interface provided on freescale? s 683xx family of parts. the on-chip breakpoint resources incl ude a total of 6 programmable regi sters?a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit pc register plus a 32-bit pc mask register. these regi sters can be accessed through the dedicated debug serial communi cation channel or from the proces sor?s supervisor mode programming model. the breakpoint registers can be configured to generate triggers by combining the address, data, and pc conditions in a variety of singl e or dual-level definitions. the tr igger event can be programmed to generate a processor halt or in itiate a debug interrupt exception.
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 features freescale semiconductor 8 to support program trace, the version 2 debug m odule provides processor status (pst[3:0]) and debug data (ddata[3:0]) ports. these bus es and the pstclk output provide ex ecution status, captured operand data, and branch target addresses defining processor activity at the cpu?s clock rate. 3.4 jtag the mcf5271 supports circuit board test strategies based on the test technol ogy committee of ieee and the joint test action group (jtag). th e test logic includes a test acces s port (tap) consisting of a 16-state controller, an instruction register , and three test registers (a 1-bi t bypass register, a 330-bit boundary-scan register, and a 32-bit id register). the boundary scan register links the device?s pins into one shift register. test logic, implemented using st atic logic design, is independen t of the device system logic. the mcf5271 implementation can do the following: ? perform boundary-scan operations to test circuit board electrical continuity ? sample mcf5271 system pins during operation and transparently shift out the result in the boundary scan register ? bypass the mcf5271 for a given circuit board test by effectively reducing the boundary-scan register to a single bit ? disable the output drive to pi ns during circuit-board testing ? drive output pins to stable levels 3.5 on-chip memories 3.5.1 cache the 8-kbyte cache can be configured into one of three possible organizations: an 8-kbyte instruction cache, an 8-kbyte data cache or a split 4-kbyte inst ruction/4-kbyte data cach e. the configuration is software-programmable by control bits within the privileged cache conf iguration register (cacr). in all configurations, the cache is a dire ct-mapped single-cycle memory, orga nized as 512 lines, each containing 16 bytes of data. the memories cons ist of a 512-entry tag array (containi ng addresses and c ontrol bits) and a 8-kbyte data array, organized as 2048 x 32 bits. if the desired address is mapped into the cache memory , the output of the data array is driven onto the coldfire core's local data bus, completing the access in a single cycle. if the data is not mapped into the tag memory, a cache miss occurs and the processor co re initiates a 16-byte line-sized fetch. the cache module includes a 16-byte line fill buffer used as te mporary storage during miss processing. for all data cache configurations, the memory operates in write-through mode and all operand writ es generate an external bus cycle. 3.5.2 sram the sram module provides a genera l-purpose 64-kbyte memory block that the coldfire core can access in a single cycle. the location of the memory bloc k can be set to any 64-k byte boundary within the 4-gbyte address space. the memory is ideal for storing critical code or data st ructures, for use as the
features mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 9 system stack, or for storing fec da ta buffers. because the sram modul e is physically connected to the processor's high-speed local bus, it can quickly serv ice core-initiated accesse s or memory-referencing commands from the debug module. the sram module is also accessible by the dma and fec non- core bus masters. th e dual-ported nature of the sram makes it ideal for implementing appl ications with double-buf fer schemes, where the processor and a dma device operate in alternate regions of the sram to maximize system performance. as an example, system performance can be increased significantly if ethernet p ackets are moved from the fec into the sram (rather than exte rnal memory) prior to any processing. 3.6 fast ethernet controller (fec) the mcf5271?s integrated fast ethernet controller (fec) performs the full set of ieee 802.3/ethernet csma/cd media access control and channel interf ace functions. the fec supports connection and functionality for the 10/ 100 mbps 802.3 media independent interfa ce (mii). it requires an external transceiver (phy) to complete the interface to the media. 3.7 uarts the mcf5271 contains three full-duplex uarts that function independently. the three uarts can be clocked by the system bus clock, el iminating the need for an externally supplied clock. they can use dma requests on transmit-ready and receive-r eady as well as interrupt request s for servicing. flow control is only available on two of the uarts. 3.8 i 2 c bus the i 2 c bus is a two-wire, bidirectional serial bus th at provides a simple, ef ficient method of data exchange, minimizing the interconnecti on between devices. this bus is su itable for applications requiring occasional communications over a s hort distance between many devices. 3.9 qspi the queued serial peripheral interface module pr ovides a high-speed synchr onous serial peripheral interface with queued transfer capability. it allows up to 16 transfers to be queue d at once, eliminating cpu intervention between transfers. 3.10 cryptography the superset device, mcf5 271, incorporates small, fa st, dedicated hardware accelerators for random number generation, message digest and hashing, and the des, 3des, and aes block cipher functions allowing for the implementation of common internet security protocol cryptography operations with performance well in excess of software-only algorithms.
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 features freescale semiconductor 10 3.11 dma timers (dtim0-dtim3) there are four independent, dma-transfer-generat ing 32-bit timers (dtim[3:0]) on the mcf5271. each timer module incorporates a 32-bit ti mer with a separate register set for configuration and control. the timers can be configured to operate from the system clock or from an external clock source using one of the dtin n signals. if the system clock is selected, it can be divided by 16 or 1. the input clock is further divided by a user-programmable 8-bi t prescaler which clocks the actu al timer counter register (tcr n ). each of these timers can be configured for input cap ture or reference compare mode. by configuring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event or cause a dma transfer. 3.12 periodic interrupt timers (pit0-pit3) the four periodic interrupt timers (pit[3:0]) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor in tervention. each timer can either count down from the value written in its pit modulus regist er, or it can be a free-running down-counter. 3.13 software watchdog timer the watchdog timer is a 16-bit timer that facilitate s recovery from runaway code. the watchdog counter is a free-running down-counter that generates a rese t on underflow. to prevent a reset, software must periodically restart the countdown. 3.14 clock module and phase locked loop (pll) the clock module contains a crysta l oscillator (osc), frequency modulated phase-locked loop (pll), reduced frequency divider (rfd), stat us/control registers, and control l ogic. to improve noise immunity, the pll and osc have their own power supply input s, vddpll and vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 3.15 interrupt controllers (intc0/intc1) there are two interrupt c ontrollers on the mcf5271, each of which can support up to 63 interrupt sources each for a total of 126. each interrupt controller is or ganized as 7 levels with 9 interrupt sources per level. each interrupt source has a unique in terrupt vector, and 56 of the 63 sour ces of a given controller provide a programmable level [1-7] and priority within the level. 3.16 dma controller the direct memory access (dma) cont roller module provides an efficien t way to move blocks of data with minimal processor interaction. the dma module provides four channels (dma0-dma3) that allow byte, word, longword or 16-byte burst line transfers. these transfers ar e triggered by software explicitly setting a dcr n [start] bit. other sources include the dm a timer, external sources via the dreq signal,
features mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 11 and uarts. the dma controller supports single or dua l address to off-chip de vices or dual address to on-chip devices. 3.17 external interface module (eim) the external bus interface handles the transfer of information between the core and memory, peripherals, or other processing elements in the external address space. features have been added to support external flash modules, for secondary wait st ates on reads and writes, and a si gnal to support active-low address valid (a signal on most flash memories). programmable chip-select outputs provi de signals to enable external memory and peripheral circuits, providing all handshaking a nd timing signals for automatic wait-s tate insertion and data bus sizing. base memory address and bl ock size are programmable, with some re strictions. for example, the starting address must be on a boundary that is a multiple of the block size. each chip select can be configured to provide read and write enable signals suitable for use with most popular static ra ms and peripherals. data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from us er mode access or read-only access. 3.18 sdram controller the sdram controller provides all required signa ls for glueless interfacing to a variety of jedec-compliant sdram devices. sd_sras /sd_scas address multiplexing is software configurable for different page sizes. to maintain refresh capabil ity without conflicting with concurrent accesses on the address and data buses, sd_ras , sd_scas , sd_we , sd_cs [1:0] and sd_cke are dedicated sdram signals. 3.19 reset the reset controller is provided to de termine the cause of reset, assert the appropriate reset signals to the system, and keep track of what caus ed the last reset. the power mana gement registers for the internal low-voltage detect (lvd) circuit are implemented in the reset module. there are six sources of reset: ? external ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software external reset on the rstout pin is software-assertable independent of chip reset state. there are also software-readable status flags indi cating the cause of the last reset.
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 signal descriptions freescale semiconductor 12 3.20 gpio unused bus interface and peripheral pins on the mcf5271 can be used as discrete general-purpose inputs and outputs. these are managed by a dedicated gpio module that logica lly groups all pins into ports located within a contig uous block of memory-mapped control registers. all of the pins associated with th e external bus interface may be used for several different functions. their primary function is to prov ide an external memory interface to ac cess off-chip resources. when not used for this, all of the pins may be us ed as general-purpose digital i/o pins . in some cases, the pin function is set by the operating mode, and the alte rnate pin functions are not supported. the digital i/o pins on the mcf5271 are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins. 4 signal descriptions this section describes signals that connect off chip, including a tabl e of signal properties. for a more detailed discussion of the mcf5271 signals, consult the mcf5235 reference manual (mcf5235rm). 4.1 signal properties table 2 lists all of the signals grouped by function. the ?dir? column is the direction for the primary function of the pin. refer to section 7, ?mechanicals/pinouts and part numbers ,? for package diagrams. note in this table and throug hout this document a singl e signal within a group is designated without square brackets (i.e., a24), wh ile designations for multiple signals within a group use br ackets (i.e., a[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is not necessarily its de fault functionality. pins that are muxed with gpio will default to their gpio functionality. table 2. mcf5270 and mcf5271 signal information and muxing signal name gpio alternate 1 alternate 2 dir. 1 mcf5270 mcf5271 160 qfp mcf5270 mcf5271 196 mapbga reset reset ? ? ? i 83 n13 rstout ? ? ? o 82 p13 clock extal ? ? ? i 86 m14 xtal ? ? ? o 85 n14
signal descriptions mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 13 clkout ? ? ? o 89 k14 mode selection clkmod[1:0] ? ? ? i 20,21 g5,h5 rcon ? ? ? i 79 k10 external memory interface and ports a[23:21] paddr[7:5] cs [6:4] ? o 126, 125, 124 b11, c11, d11 a[20:0] ? ? ? o 123:115, 112:106, 102:98 a12, b12, c12, a13, b13, b14, c13, c14, d12, d13, d14, e11, e12, e13, e14, f12, f13, f14, g11, g12, g13 d[31:16] ? ? ? o 22:30, 33:39 g1, g2, h1, h2, h3, h4, j1, j2, j3, j4, k1, k2, k3, k4, l1, l2 d[15:8] pdatah[7:0] ? ? o 42:49 m1, n1, m2, n2, p2, l3, m3, n3 d[7:0] pdatal[7:0] ? ? o 50:52, 56:60 p3, m4, n4, p4, l5, m5, n5, p5 bs [3:0] pbs[7:4] cas [3:0] ? o 143:140 b6, c6, d7, c7 oe pbusctl7 ? ? o 62 n6 ta pbusctl6 ? ? i 96 h11 tea pbusctl5 dreq1 ?i ?j14 r/w pbusctl4 ? ? o 95 j13 tsiz1 pbusctl3 dack1 ? o ?p6 tsiz0 pbusctl2 dack0 ? o ?p7 ts pbusctl1 dack2 ? o 97 h13 tip pbusctl0 dreq0 ? o ?h12 chip selects cs [7:4] pcs[7:4] ? ? o ? b9, a10, c10, a11 cs [3:2] pcs[3:2] sd_cs[1:0] ? o 132,131 a9, c9 cs1 pcs1 ? ? o 130 b10 cs0 ? ? ? o 129 d10 sdram controller table 2. mcf5270 and mcf5271 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5270 mcf5271 160 qfp mcf5270 mcf5271 196 mapbga
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 signal descriptions freescale semiconductor 14 sd_we psdram5 ? ? o 92 k13 sd_scas psdram4 ? ? o 91 k12 sd_sras psdram3 ? ? o 90 k11 sd_cke psdram2 ? ? o 139 e8 sd_cs [1:0] psdram[1:0] ? ? o ? l12, l13 external interrupts port irq [7:3] pirq[7:3] ? ? i irq7=63 irq4=64 n7, m7, l7, p8, n8 irq2 pirq2 dreq2 ? i ?m8 irq1 pirq1 ? ? i 65 l8 fec emdc pfeci2c3 i2c_scl u2txd o 151 d4 emdio pfeci2c2 i2c_sda u2rxd i/o 150 d5 ecol ? ? ? i 9 e2 ecrs ? ? ? i 8 e1 erxclk ? ? ? i 7 d1 erxdv ? ? ? i 6 d2 erxd[3:0] ? ? ? i 5:2 d3, c1, c2, b1 erxer ? ? ? o 159 b2 etxclk ? ? ? i 158 a2 etxen ? ? ? i 157 c3 etxer ? ? ? o 156 b3 etxd[3:0] ? ? ? o 155:152 a3, a4, c4, b4 i 2 c i2c_sda pfeci2c1 ? ? i/o ?j12 i2c_scl pfeci2c0 ? ? i/o ?j11 dma dack [2:0] and dreq [2:0] do not have a dedicated bond pads. please refer to the following pins for muxing: ts and dt2out for dack2 , tsiz1and dt1out for dack1 , tsiz0 and dt0out for dack0 , irq2 and dt2in for dreq2 , tea and dt1in for dreq1 , and tip and dt0in for dreq0 . ? ? qspi qspi_cs1 pqspi4 sd_cke ? o ?b7 table 2. mcf5270 and mcf5271 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5270 mcf5271 160 qfp mcf5270 mcf5271 196 mapbga
signal descriptions mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 15 qspi_cs0 pqspi3 ? ? o 146 a6 qspi_clk pqspi2 i2c_scl ? o 147 c5 qspi_din pqspi1 i2c_sda ? i 148 b5 qspi_dout pqspi0 ? ? o 149 a5 uarts u2txd puarth1 ? ? o ?a8 u2rxd puarth0 ? ? i ?a7 u1cts puartl7 u2cts ? i 136 b8 u1rts puartl6 u2rts ? o 135 c8 u1txd puartl5 ? ? o 133 d9 u1rxd puartl4 ? ? i 134 d8 u0cts puartl3 ? ? i 12 f3 u0rts puartl2 ? ? o 15 g3 u0txd puartl1 ? ? o 14 f1 u0rxd puartl0 ? ? i 13 f2 dma timers dt3in ptimer7 u2cts ? i ?h14 dt3out ptimer6 u2rts ? o ?g14 dt2in ptimer5 dreq2 dt2out i 66 m9 dt2out ptimer4 dack2 ? o ?l9 dt1in ptimer3 dreq1 dt1out i 61 l6 dt1out ptimer2 dack1 ? o ?m6 dt0in ptimer1 dreq0 ? i 10 e4 dt0out ptimer0 dack0 ? o 11 f4 bdm/jtag 2 dsclk ? trst ? o 70 n9 pstclk ? tclk ? o 68 p9 bkpt ? tms ? o 71 p10 dsi ? tdi ? i 73 m10 dso ? tdo ? o 72 n10 jtag_en ? ? ? i 78 k9 ddata[3:0] ? ? ? o ? m12, n12, p12, l11 table 2. mcf5270 and mcf5271 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5270 mcf5271 160 qfp mcf5270 mcf5271 196 mapbga
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 modes of operation freescale semiconductor 16 5 modes of operation 5.1 chip configuration mode?device operating options ? chip operating mode: ? master mode ? boot device/size: ? external device boot ? 32-bit ? 16-bit (default) ?8-bit ? output pad strength: pst[3:0] ? ? ? o 77:74 m11, n11, p11, l10 test test ? ? ? i 19 f5 pll_test ? ? ? i ? power supplies vddpll ? ? ? i 87 m13 vsspll ? ? ? i 84 l14 ovdd ? ? ? i 1, 18, 32, 41, 55, 69, 81, 94, 105, 114, 128, 138, 145 e5, e7, e10, f7, f9, g6, g8, h7, h8, h9, j6, j8, j10, k5, k6, k8 vss ? ? ? i 17, 31, 40, 54, 67, 80, 88, 93, 104, 113, 127, 137, 144, 160 a1, a14, e6, e9, f6, f8, f10, g7, g9, h6, j5, j7, j9, k7, p1, p14 vdd ? ? ? i 16, 53, 103 d6, f11, g4, l4 notes: 1 refers to pin?s primary function. all pins which are configurable for gpio have a pullup enabled in gpio mode with the exception of pbus ctl[7], pbusctl[4:0], paddr, pbs, psdram. 2 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the gpio module is not responsible for assigning these pins. table 2. mcf5270 and mcf5271 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5270 mcf5271 160 qfp mcf5270 mcf5271 196 mapbga
modes of operation mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 17 ? partial drive strength (default) ? full drive strength ? clock mode: ? normal pll with external crystal ? normal pll with external clock ? 1:1 pll mode ? external oscillator mode (no pll) ? chip select configuration: ? paddr[7:5] configured as chip select(s) and/or address line(s) ? paddr[7:5] configured as a23-a21 (default) ? paddr configured as cs6 , paddr[6:5] as a22-a21 ? paddr[7:6] configured as cs [6:5], paddr5 as a21 ? paddr[7:5] configured as cs [6:4] 5.1.1 chip configuration pins table 3. configuration pin descriptions pin chip configuration function pin state/meaning comments rcon chip configuration enable 1 disabled 0 enabled active low: if asserted, then all configuration pins must be driven appropriately for desired operation d16 select chip operating mode 1master 0 reserved d20, d19 select external boot device data port size 00,11 external (32-bit) 10 external (8-bit) 01 external (16-bit) value read defaults to 32-bit d21 select output pad drive strength 1full 0 partial clkmod1, clkmod0 select clock mode 00 external clock mode (no pll) 01 1:1 pll mode 10 normal pll with external clock reference 11 normal pll with crystal clock reference vddpll must be supplied if a pll mode is selected
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 modes of operation freescale semiconductor 18 5.2 low power modes the following features are available to su pport applications which require low power. ? four modes of operation: ?run ?wait ? doze ?stop ? ability to shut down most peripherals independently. ? ability to shut down the external clkout pin. there are four modes of operation: run, wait, doze, and stop. the system enters a low power mode when the user programs the low power bits (lpmd) in the lpcr (low power control register) in the cim before the cpu core executes a stop instruction. this idles the cpu with no cycles active. the lpmd bits indicate to the system and clock controll er to power down and stop the clocks appropriately. during stop mode, the system clock is stopped low. a wakeup event is required to exit a low power m ode and return back to run mode. wakeup events consist of any of the followi ng conditions. see the following sections for more details. 1. any type of reset. 2. assertion of the bkpt pin to request entry into debug mode. 3. debug request bit in the bdm control regi ster to request entry into debug mode. 4. any valid interrupt request. 5.2.1 run mode run mode is the normal system opera ting mode. current consumption in th is mode is related directly to the frequency chosen for the system clock. d25, d24 select chip select / address line 00 paddr[7:5] configured as a23-a21 (default) 10 paddr7 configured as cs6 , paddr[6:5] as a22-a21 01 paddr[7:6] configured as cs [6:5], paddr5 as a21 11 paddr[7:5] configured as cs [6:4] jtag_en selects bdm or jtag mode 0bdm mode 1 jtag mode table 3. configuration pin descriptions (continued) pin chip configuration function pin state/meaning comments
design recommendations mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 19 5.2.2 wait mode wait mode is intended to be used to stop only the cpu core and memory clocks until a wakeup event is detected. in this mode, peripherals may be programme d to continue ope rating and can generate interrupts, which cause the cpu core to exit from wait mode. 5.2.3 doze mode doze mode affects the cpu core in the same manner as wait mode, but with a different code on the cim lpmd bits, which are monitore d by the peripherals. each periphe ral defines individual operational characteristics in doze mode. periphe rals which continue to run and have the capability of producing interrupts may cause the cpu to exit the doze mode and return to the run m ode. peripherals which are stopped will restart operation on exit from do ze mode as defined for each peripheral. 5.2.4 stop mode stop mode affects the cpu core in the same manner as the wait and doze modes, but with a different code on the ccm lpmd bits. in this mode, all clocks to the system are stopped and the peripherals cease operation. stop mode must be entered in a controlled manne r to ensure that any current operation is properly terminated. when exiting stop mode, most peripherals retain their pre-stop st atus and resume operation. 5.2.5 peripheral shut down most peripherals may be disa bled by software in order to cease in ternal clock generati on and remain in a static state. each peripheral has its own specific disabling sequence (r efer to each peripheral description for further details). a peri pheral may be disabled at anytime and will remain disabled during any low power mode of operation. 6 design recommendations 6.1 layout ? use a 4-layer printed circuit board with the v dd and gnd pins connected directly to the power and ground planes for the mcf5271. ? see application note an1259 system design and layout techniques for noise reduction in processor-based systems. ? match the pc layout trace wi dth and routing to match trace length to operating frequency and board impedance. add terminat ion (series or therein) to the traces to dampen reflections. increase the pcb impedance (if possible) keepi ng the trace lengths balanced and short. then do cross-talk analysis to separate traces with significant parallelis m or are otherwise "noisy". use 6 mils trace and separation. clocks get extr a separation and more precise balancing.
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 design recommendations freescale semiconductor 20 6.2 power supply ?33 f, .1 f and .01 f across each power supply 6.3 decoupling ? place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. ?.1 f and .01 f at each supply input 6.4 buffering ? use bus buffers on all data/address lines for al l off-board accesses and for all on-board accesses when excessive loading is expected. see section 8, ?preliminary electrical characteristics .? 6.5 pull-up recommendations ? use external pull-up resistors on unused inputs. see pin table. 6.6 clocking recommendations ? use a multi-layer board wi th a separate ground plane. ? place the crystal and all other associated components as close to the extal and xtal (oscillator pins) as possible. ? do not run a high frequency trace around crystal circuit. ? ensure that the ground for the bypass capaci tors is connected to a solid ground trace. ? tie the ground trace to the ground pin nearest extal and xtal. this prevents large loop currents in the vicinity of the crystal. ? tie the ground pin to the most solid ground in the system. ? do not connect the trace that connects the oscill ator and the ground plane to any other circuit element. this tends to ma ke the oscillator unstable. ? tie xtal to ground when an external oscillator is clocking the device. 6.7 interface recommendations 6.7.1 sdram controller 6.7.1.1 sdram controller signals in synchronous mode table 4 shows the behavior of sdram signals in synchronous mode.
design recommendations mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 21 6.7.1.2 address multiplexing table 5 shows the generic address mul tiplexing scheme for sdram confi gurations. all po ssible address connection configurations can be derived from this table. table 4. synchronous dram signal connections signal description sd_sras synchronous row address strobe. indicates a va lid sdram row address is present and can be latched by the sdram. sd_sras should be connected to the corresponding sdram sd_sras . do not confuse sd_sras with the dram controller?s sd_cs [1:0], which should not be interfaced to the sdram sd_sras signals. sd_scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. sd_scas should be connected to the corresponding signal labeled sd_scas on the sdram. dramw dram read/write. asserted for write operations and negated for read operations. sd_cs [1:0] row address strobe. select each memory block of sdrams connected to the mcf5271. one sd_cs signal selects one sdram block and connects to the corresponding cs signals. sd_cke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode where operations are su spended or they can enter self-refresh mode. sd_cke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows sd_cke to prov ide command-bit functionality. bs [3:0] column address strobe. for synchronous operation, bs [3:0] function as byte enables to the sdrams. they connect to the dqm signals (or mask qualifiers) of the sdrams. clkout bus clock output. connects to the clk input of sdrams. table 5. generic address multiplexing scheme address pin row address column address notes related to port sizes 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used 20 20 19
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 design recommendations freescale semiconductor 22 the following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for inte rfacing the mcf5271 to sdram. to use the tables, find the one that corresponds to the number of column address lines on the sdram and to the port size as seen by the mcf5271, which is not necessarily the sdram port size. for exampl e, if two 1m x 16-bit sdrams together form a 2m x 32-bit memory, the port size is 32 bits. most sdrams likely have fewer address lines than are shown in the tables, so follow onl y the connections shown until all sdram address lines are connected. 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 table 6. mcf5271 to sdram interface (8-bit port, 9-column address lines) mcf5271 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a2 0a21a22a23a24a25a26a27a28a29a30a31 row 17 16 15 14 13 12 11 10 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 column 012345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 7. mcf5271mcf5271 to sdram interfa ce (8-bit port,10-column address lines) mcf5271 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19202122232425262728293031 column 01234567818 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 8. mcf5271mcf5271 to sdram interface (8-bit port,11-column address lines) mcf5271 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 192122232425262728293031 column 0123456781820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 table 5. generic address multiplexing scheme (continued) address pin row address column address notes related to port sizes
design recommendations mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 23 table 9. mcf5271mcf5271 to sdram interfac e (8-bit port,12-column address lines) mcf5271 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 1921232425262728293031 column 012345678182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 10. mcf5271mcf5271 to sdram interface (8-bit port,13-column address lines) mcf5271 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19212325262728293031 column 01234567818202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 11. mcf5271mcf5271 to sdram interface (16-bit port, 8-column address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 column 12345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 12. mcf5271mcf5271 to sdram interface (16-bit port, 9-column address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 column 1234567817 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 13. mcf5271mcf5271 to sdram interface (16-bit port, 10-column address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202122232425262728293031 column 123456781719 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 design recommendations freescale semiconductor 24 table 14. mcf5271mcf5271 to sdram interface (16-bit port, 11-column address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 20 22 23 24 25 26 27 28 29 30 31 column 1 2 3 4 5 6 7 8 17 19 21 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 15. mcf5271mcf5271 to sdram interfac e (16-bit port, 12-column address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a25 a26 a27 a28 a29 a30 a31 row 16 15 14 13 12 11 10 9 18 20 22 24 25 26 27 28 29 30 31 column 1234567817192123 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 16. mcf5271mcf5271 to sdram interf ace (16-bit port, 13-c olumn-address lines) mcf5271 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202224262728293031 column 1 2 3 4 5 6 7 8 17 19 21 23 25 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 17. mcf5271mcf5271 to sdram interface (32-bit port, 8-column address lines) mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a2 1a22a23a24a25a26a27a28a29a30a31 row 151413121110 9 171819202122232425262728293031 column 234567816 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 18. mcf5271mcf5271 to sdram interfa ce (32-bit port, 9-co lumn address lines) mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719202122232425262728293031 column 23456781618 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20
design recommendations mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 25 6.7.1.3 sdram interfacing example the tables in the previous section can be used to configure the interface in the following example. to interface one 2m 32-bit 4 bank sdram component (8 columns) to the mcf5271, the connections would be as shown in table 22 . 6.7.2 ethernet phy transceiver connection the fec supports both an mii interfac e for 10/100 mbps ethernet and a se ven-wire serial interface for 10 mbps ethernet. the interface mode is select ed by r_cntrl[mii_mode]. in mii mode, the 802.3 standard defines and the fec module s upports 18 signals. these are shown in table 23 . table 19. mcf5271mcf5271 to sdram interface (32-bit port, 10-column address lines) mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 17192122232425262728293031 column 2345678161820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 table 20. mcf5271mcf5271 to sdram interface (32-bit port, 11-column address lines) mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 15 14 13 12 11 10 9 17 19 21 23 24 25 26 27 28 29 30 31 column 234567816182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 21. mcf5271mcf5271 to sdram interface (32-bit port, 12-column address lines) mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719212325262728293031 column 2 3 4 5 6 7 8 1618202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 22. sdram hardware connections sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 mcf5271 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 design recommendations freescale semiconductor 26 the serial mode interface operates in what is generally referred to as amd mode. the mcf5271 configuration for seven-wire seri al mode connections to the exte rnal transceiver are shown in table 24 . refer to the m5271evb evaluation board user?s manual for an example of how to connect an external phy. schematics for this board are accessi ble at the mcf5271 site by navigating to: http://www.freescale.com . table 23. mii mode signal description mcf5271 pin transmit clock etxclk transmit enable etxen transmit data etxd[3:0] transmit error etxer collision ecol carrier sense ecrs receive clock erxclk receive enable erxdv receive data erxd[3:0] receive error erxer management channel clock emdc management channel serial data emdio table 24. seven-wire mode configuration signal description mcf5271 pin transmit clock etxclk transmit enable etxen transmit data etxd[0] collision ecol receive clock erxclk receive enable erxdv receive data erxd[0] unused, configure as pb14 erxer unused input, tie to ground ecrs unused, configure as pb[13:11] erxd[3:1] unused output, ignore etxer unused, configure as pb[10:8] etxd[3:1] unused, configure as pb15 emdc input after reset, connect to ground emdio
mechanicals/pi nouts and part numbers mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 27 6.7.3 bdm use the bdm interface as shown in the m5271evb ev aluation board user?s manual. the schematics for this board are accessible at th e mcf5271 site by navigating from: http://www.freescale.com following the 32-bit embedded processors, 68k/coldfir e, mcf5xxx, mcf5271 and m5271evb links. 7 mechanicals/pinouts and part numbers this section contains drawings s howing the pinout and the packaging a nd mechanical char acteristics of the mcf5271 devices. see table 2 for a list the signal names and pin locations for each device.
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 mechanicals/pinouts and part numbers freescale semiconductor 28 7.1 pinout?196 mapbga figure 2 shows a pinout of th e mcf5270/71cvmxxx package. figure 2. mcf5270/71cvmxxx pinout (196 mapbga) 1234567891011121314 a vss etxclk etxd3 etxd2 qspi_ dout qspi_cs0 u2rxd u2txd cs3 cs6 cs4 a20 a17 vss a b erxd0 erxer etxer etxd0 qspi_din bs3 qspi_cs1 u1cts cs7 cs1 a23 a19 a16 a15 b c erxd2 erxd1 etxen etxd1 qsck bs2 bs0 rts1 cs2 cs5 a22 a18 a14 a13 c d erxclk erxdv erxd3 emdc emdio core vdd_4 bs1 u1rxd1 u1txd cs0 a21 a12 a11 a10 d e ecrs ecol nc tin0 vdd vss vdd sd_cke vss vdd a9 a8 a7 a6 e f u0txd u0rxd u0cts dtout0 test vss vdd vss vdd vss core vdd_3 a5 a4 a3 f g data31 data30 u0rts core vdd_1 clk mod1 vdd vss vdd vss nc a2 a1 a0 dtout3 g h data29 data28 data27 data26 clk mod0 vss vdd vdd vdd nc ta tip ts dtin3 h j data25 data24 data23 data22 vss vdd vss vdd vss vdd i2c_scl i2c_sda r/w tea j k data21 data20 data19 data18 vdd vdd vss vdd jtag_en rcon sd_ ras sd_ cas sd_ we clkout k l data17 data16 data10 core vdd_2 data3 dtin1 irq5 irq1 dtout2 pst0 ddata0 sd_ cs1 sd_ cs0 vsspll l m data15 data13 data9 data 6 data2 dtout1 irq6 irq2 dtin2 tdi/dsi pst3 ddata3 vddpll extal m n data14 data12 data8 data5 data1 oe irq7 irq3 trst / dsclk tdo/dso pst2 ddata2 reset xtal n p vss data11 data7 data4 data0 tsiz1 tsiz0 irq4 tclk/ pstclk tms/ bkpt pst1 ddata1 rstout vss p 1234567891011121314
mechanicals/pi nouts and part numbers mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 29 7.2 package dimensions?196 mapbga figure 3 shows mcf5270/71cvmxxx package dimensions. figure 3. 196 mapbga package dimensions (case no. 1128a-01) x 0.20 laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k q 5 view m-m e 13x s m x 0.30 y z 0.10 z 3 b 196x metalized mark for pin 1 identification in this area 14 13 12 11 5 4 3 2 b c d e f g h j k l 4 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.32 1.75 a1 0.27 0.47 a2 1.18 ref b 0.35 0.65 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc y k m n p a 1 6 10 9
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 mechanicals/pinouts and part numbers freescale semiconductor 30 7.3 pinout?160 qfp figure 4 shows a pinout of the mcf5271cabxxx package. figure 4. mcf5270/71cabxxx pinout (160 qfp) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vss erxer etxclk etxen etxer etxd3 etxd2 etxd1 etxd0 emdc emdio qspi_dout qspi_din qspi_clk qspi_cs0 o-vdd vss bs3 bs2 bs1 bs0 sd_cke/qspi_cs1 o-vdd vss u1cts u1rts u1rxd u1txd cs3 cs2 cs1 cs0 o-vdd vss a18 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 o-vdd vss a11 a10 a9 a8 a7 a6 a5 o-vdd vss core_vdd_3 a4 a3 a2 a1 a0 ts ta r/w o-vdd vss sd_we sd_scas sd_sras clkout vss vddpll extal xtal vsspll reset rstout o-vdd a23 o-vdd erxd0 erxd1 erxd2 erxd3 erxdv erxclk ecrs ecol u0tin u0tout u0cts u0rxd u0txd u0rts core vdd_1 vss o-vdd test clkmod1 clkmod0 data31 data30 data29 data28 data27 data26 data25 data24 data23 vss o-vdd data22 data21 data20 data19 data18 data17 data16 vss o-vdd data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 core vdd_2 vss o-vdd data4 data3 data2 data1 data0 dtin1 oe irq7 irq4 irq1 dtin2 vss tclk\pstclk o-vdd trst/dsclk tms\bkpt tdo/dso tdi/dsi pst0 pst1 pst2 pst3 jtag_en rcon vss mcf5271
mechanicals/pi nouts and part numbers mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 31 7.4 package dimensions?160 qfp figure 5 shows mcf5270/71cab80 package dimensions. figure 5. 160 qfp package dimensions top & bottom case 864a-03 d n f j base metal section b?b detail c s s ?c? e c m u w k x q r t h ?h? b ?a?, ?b?, ?d? b detail a g p s s s s s s a s l z l y detail a b v ?a? ?b? ?h? detail c millimeters inches dim min max min max a b c d e f g h j k l m n p q r t u v w x y z 27.90 28.10 1.098 1.106 27.90 28.10 1.098 1.106 3.35 3.85 0.132 1.106 3.35 3.85 0.009 0.015 0.22 0.38 0.009 0.013 0.22 0.33 0.126 0.138 3.20 3.50 0.65 bsc 0.026 ref 0.010 0.014 0.25 0.35 0.004 0.009 0.11 0.23 0.028 0.035 0.70 0.90 25.35 bsc 0.998 ref 5 q 16 q 5 q 16 q 0.004 0.007 0.11 0.19 0.325 bsc 0.013 ref 0 q 7 q 0 q 7 q 0.005 0.012 0.13 0.30 0.005 ? 0.13 ? 0 q ?0 q ? 31.00 31.40 1.220 1.236 s 31.00 31.40 1.220 1.236 0.016 ? 0.4 ? 1.60 ref 0.063 ref 1.33 ref 0.052 ref 1.33 ref 0.052 ref notes 1. dimensioning and tolerincing per ansi y14.5m, 1982. 2. controlling dimension: millimeter 3. datum plan -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b-, and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 0.110 (0.004) a-b d c 0.13 (0.005) m 0.20 (0.008) a-b d c m m 0.20 (0.008) a-b 0.20 (0.008) a-b d c s s m m h a-b d h a-b d 0.20 (0.008) 0.20 (0.008) 0.20 (0.008) a-b
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 32 7.5 ordering information 8 preliminary electrical characteristics this chapter contains electrical specification tabl es and reference timing diagrams for the mcf5271 microcontroller unit. this section contains deta iled information on power considerations, dc/ac electrical characteristi cs, and ac timing spec ifications of mcf5271. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specificat ions will be met. finalized speci fications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this pr ocessor document supersede any values found in the module specifications. 8.1 maximum ratings table 25. orderable part numbers freescale part number description speed temperature pcf5270ab100 mcf5270 risc microprocessor, 160 qfp 100mhz 0 q to +70 q c pcf5270vm100 mcf5270 risc microprocessor, 196 mapbga 100mhz 0 q to +70 q c PCF5271cab100 mcf5271 risc microprocessor, 160 qfp 100mhz -40 q to +85 q c PCF5271cvm100 mcf5271 risc microprocessor, 196 mapbga 100mhz -40 q to +85 q c table 26. absolute maximum ratings 1, 2 notes: 1 functional operating conditions are given in dc electrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. continued operation at these levels may affect device reliability or cause permanent damage to the device. rating symbol value unit core supply voltage v dd ? 0.5 to +2.0 v pad supply voltage ov dd ? 0.3 to +4.0 v clock synthesizer supply voltage v ddpll ? 0.3 to +4.0 v digital input voltage 3 v in ? 0.3 to + 4.0 v instantaneous maximum current single pin limit (applies to all pins) 3,4,5 i d 25 ma operating temperatur e range (packaged) t a (t l - t h ) ? 40 to 85 q c storage temperature range t stg ? 65 to 150 q c
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 33 8.2 thermal characteristics table 27 lists thermal resistance values 2 this device contains circuitry protecting a gainst damage due to high static voltage or electrical fields; however, it is advised that no rmal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or ov dd ). 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 all functional non-supply pins are internally clamped to v ss and ov dd . 5 power supply must maintain regulation within operating ov dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ov dd ) is greater than i dd , the injection current may flow out of ov dd and could result in external power supply going out of regulation . insure external ov dd load will shunt current greater than maximum injection current. this will be the greatest risk when the processor is not consuming power (ex; no clock).power supply must maintain regulation within operating ov dd range during instantaneous and operating maximum current conditions. table 27. thermal characteristics characteristic symbol 196 mapbga 160qfp unit junction to ambient, natural convection four layer board (2s2p) t jma 32 1,2 notes: 1 t jma and < jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. motorola recommends the use of t jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rat ed specification. system des igners should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specif ication can be verified by physical measurement in the customer?s system using the < jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 40 3,4 3 t jma and < jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. motorola recommends the use of t jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rat ed specification. system des igners should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specif ication can be verified by physical measurement in the customer?s system using the < jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 4 per jedec jesd51-6 with the board horizontal. q c / w junction to ambient (@200 ft/min) four layer board (2s2p) t jma 29 5 , 6 36 5 , 6 q c / w junction to board t jb 20 5 5 thermal resistance between the die and the printed circuit board in conformance with jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 25 6 6 thermal resistance between the die and the printed circuit board in conformance with jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. q c / w junction to case t jc 10 7 10 8 q c / w junction to top of package < jt 2 5 ,9 2 5 ,10 q c / w maximum operating junction temperature t j 104 105 o c
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 34 8.3 dc electrical specifications 7 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 8 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 9 thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. 10 thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. the average chip-junction temperature (t j ) in q c can be obtained from: (1) where: t a = ambient temperature, q c 4 jma = package thermal resistance, junction-to-ambient, q c/w p d = p int p i/o p int = i dd u v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o p int and can be ignored. an appr oximate relations hip between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d u (t a + 273 q c) + 4 jma u p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . table 28. dc electrical specifications 1 characteristic symbol min typical max unit core supply voltage v dd 1.35 ? 1.65 v pad supply voltage ov dd 3?3.6v input high voltage v ih 0.7 ov dd ?3.65v input low voltage v il v ss ? 0.3 ? 0.35 ov dd v input hysteresis v hys 0.06 ov dd ??mv input leakage current v in = v dd or v ss , input-only pins i in ?1.0 ? 1.0 p a t j t a p d 4 jma u + = p d kt j 273 q c + y =
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 35 high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz ?1.0 ? 1.0 p a output high voltage (all input/ output and all output pins) i oh = ?5.0 ma v oh ov dd - 0.5 ? __ v output low voltage (all inpu t/output and all output pins) i ol = 5.0ma v ol __ ? 0.5 v weak internal pull up device current, tested at v il max. 2 i apu ?10 ? ? 130 p a input capacitance 3 all input-only pins all input/output (three-state) pins c in ? ? ? 7 7 pf load capacitance 4 low drive strength high drive strength c l ? 25 50 pf core operating supply current 5 master mode i dd ? 135 150 ma pad operating supply current master mode low power modes oi dd ? ? 100 tbd ? ? ma p a dc injection current 3, 6, 7, 8 v negclamp =v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total processor limit, include s sum of all stressed pins i ic ?1.0 ?10 1.0 10 ma notes: 1 refer to table 29 for additional pll specifications. 2 refer to the mcf5271 signals section for pins having weak internal pull-up devices. 3 this parameter is characterized before qualification rather than 100% tested. 4 pf load ratings are based on dc loading and are provided as an indication of driver strength. high speed interfaces require transmission line analysis to determine proper drive strength and termination. see high speed signal propagation: advanced black magic by howard w. johnson for design guidelines. 5 current measured at maximum system clock frequency, all modu les active, and default drive strength with matching load. 6 all functional non-supply pins are internally clamped to v ss and their respective v dd . 7 input must be current limited to the value specified. to dete rmine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. insure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the pr ocessor is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would r educe overall power consumption. also, at power-up, system clock is not present during the power-up sequence until the pll has attained lock. table 28. dc electrical specifications 1 (continued) characteristic symbol min typical max unit
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 36 8.4 oscillator and pllmrfm electrical characteristics table 29. hip7 pllmrfm electrical specifications 1 notes: 1 all values given are initial design targets and subject to change. num characteristic symbol min. value max. value unit 1 pll reference frequency range crystal reference external reference 1:1 mode (note: f sys/2 = 2 u f ref_1:1 ) f ref_crystal f ref_ext f ref_1:1 8 8 24 25 25 50 mhz 2 core frequency clkout frequency 2 external reference on-chip pll frequency 2 all internal registers retain data at 0 hz. f sys f sys/2 0 f ref / 32 100 50 50 mhz mhz mhz 3 loss of reference frequency 3, 5 3 ?loss of reference frequency? is the reference fre quency detected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz 4 self clocked mode frequency 4, 5 4 self clocked mode frequency is the frequency that th e pll operates at when the reference frequency falls below f lor with default mfd/rfd settings. f scm 10.25 15.25 mhz 5 crystal start-up time 5, 6 5 this parameter is guaranteed by characteriza tion before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. t cst ?10ms 6 xtal load capacitance 5 530pf 7 pll lock time 5, 7,13 t lpll ?750 p s 8 power-up to lock time 5, 6,8 with crystal reference (includes 5 time) without crystal reference 9 t lplk ? ? 11 750 ms p s 9 1:1 mode clock skew (between clkout and extal) 10 t skew ?1 1 ns 10 duty cycle of reference 5 t dc 40 60 % 11 frequency un-lock range f ul ?3.8 4.1 % f sys/2 12 frequency lock range f lck ?1.7 2.0 % f sys/2 13 clkout period jitter, 5, 6, 8,11, 12 measured at f sys/2 max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5.0 .01 % f sys/2 14 frequency modulation range limit 13 , 14 (f sys/2 max must not be exceeded) c mod 0.8 2.2 %f sys/2 15 ico frequency. f ico = f ref * 2 * (mfd+2) 15 f ico 48 75 mhz
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 37 8.5 external interface timing characteristics table 30 lists processor bus input timings. note all processor bus timings are synchr onous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived fro m these values. 7 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesiz er control register (syncr). 8 assuming a reference is available at power up , lock time is measured from the time v dd and v ddsyn are valid to rstout negating. if the crystal oscillator is being us ed as the reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 9 t lpll = (64 * 4 * 5 + 5 w ) t ref , where t ref = 1/f ref_crystal = 1/f ref_ext = 1/f ref_1:1 , and w = 1.57x10 -6 2(mfd + 2). 10 pll is operating in 1:1 pll mode. 11 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys/2 . measurements are made with the device po wered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. 12 values are with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of cjitter+cmod. 13 modulation percentage applies over an interval of 10 p s, or equivalently the modulation rate is 100khz. 14 modulation rate selected must not result in f sys/2 value greater than the f sys/2 maximum specified value. modulation range determined by hardware design. 15 f sys/2 = f ico / (2 * 2 rfd ) table 30. processor bus input timing specifications name characteristic 1 notes: 1 timing specifications are tested using full drive st rength pad configurations in a 50ohm transmission line environment.. symbol min max unit freq system bus frequency f sys/2 50 50 mhz b0 clkout period t cyc 1/50 ns control inputs b1a control input valid to clkout high 2 2 tea and ta pins are being referred to as control inputs. t cvch 9?ns b1b bkpt valid to clkout high 3 3 refer to figure a-19. t bkvch 9?ns b2a clkout high to control inputs invalid 2 t chcii 0?ns b2b clkout high to asynch ronous cont rol input bkpt invalid 3 t bknch 0?ns data inputs b4 data input (d[31:0]) valid to clkout high t divch 4?ns b5 clkout high to data input (d[31:0]) invalid t chdii 0?ns
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 38 timings listed in table 30 are shown in figure 6 & figure a-3. figure 6. general input timing requirements 8.6 processor bus output timing specifications table 31 lists processor bus output timings. table 31. external bus output timing specifications name characteristic symbol min max unit control outputs b6a clkout high to chip selects valid 1 t chcv ?0.5t cyc +5 ns b6b clkout high to byte enables (bs [3:0]) valid 2 t chbv ?0.5t cyc +5 ns b6c clkout high to output enable (oe ) valid 3 t chov ?0.5t cyc +5 ns b7 clkout high to control output (bs [3:0], oe ) invalid t chcoi 0.5t cyc +1.5 ? ns b7a clkout high to chip selects invalid t chci 0.5t cyc +1.5 ? ns invalid invalid clkout(75mhz) t setup t hold input setup and hold 1.5v trise v h = v ih v l = v il 1.5v 1.5v valid tfall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs clkout b4 b5
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 39 read/write bus timings listed in table 31 are shown in figure 7 , figure 8 , and figure 9 . address and attribute outputs b8 clkout high to address (a[23:0]) and control (ts , tsiz [1:0], tip , r/w) valid t chav ?9ns b9 clkout high to address (a[23:0]) and control (ts , tsiz [1:0], tip , r/w) invalid t chai 1.5 ? ns data outputs b11 clkout high to data output (d[31:0]) valid t chdov ?9ns b12 clkout high to data output (d[31:0]) invalid t chdoi 1.5 ? ns b13 clkout high to data output (d[31:0]) high impedance t chdoz ?9ns notes: 1 cs transitions after the falling edge of clkout. 2 bs transitions after the falling edge of clkout. 3 oe transitions after the falling edge of clkout. table 31. external bus output timing specifications (continued) name characteristic symbol min max unit
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 40 figure 7. read/write (internally terminated) sram bus timing b12 b13 b8 clkout csn a[23:0] r/w bs [3:0] d[31:0] ta (h) (h) s0 s2 s3 s1 s4 s5 s0 s1 s2 s3 s4 s5 tea (h) b6a b8 b7a b6c b7 b6b b7 b4 b5 b11 b9 b9 b6b oe b0 b7 b9 ts tip b8 b8 b9 b8 b9 tsiz [1:0] b7a b6a b8
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 41 figure 8 shows a bus cycle terminated by ta showing timings listed in table 31 . figure 8. sram read bus cycle terminated by ta b8 b9 b6a clkout csn a[23:0] oe r/w bs [3:0] ta (h) s0 s2 s3 s1 s4 s5 s0 s1 tea (h) b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b4 b5 b8 ts b9 tip tsiz[ 1:0]
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 42 figure 9 shows an sram bus cycle terminated by tea showing timings listed in table 31 . figure 9. sram read bus cycle terminated by tea clkout csn a[23:0] oe r/w bs [3:0] tea (h) s0 s2 s3 s1 s4 s5 s0 s1 ta (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b8 b9 ts b9 tip b8 tsiz[ 1:0]
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 43 figure 10 shows an sdram read cycle. figure 10. sdram read cycle table 32. sdram timing num characteristic symbol min max unit d1 clkout high to sdram address valid t chdav ?9ns d2 clkout high to sdram control valid t chdcv ?9ns d3 clkout high to sdram address invalid t chdai 1.5 ? ns d4 clkout high to sdram control invalid t chdci 1.5 ? ns d5 sdram data valid to clkout high t ddvch 4?ns d6 clkout high to sdram data invalid t chddi 1.5 ? ns d7 1 notes: 1 d7 and d8 are fo r write cycles only. clkout high to sdram data valid t chddvw ?9ns d8 2 clkout high to sdram data invalid t chddiw 1.5 ? ns a[23:0] ras d[31:0] actv nop pall nop ras [1:0] read column sd_cke 0 sdwe cas [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d1 d2 d4 d6 d5 d4 d4 1 dacr[casl] = 2 cas 1 nop d4 row d3 d2 d2 d2 d2
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 44 figure 11 shows an sdram write cycle. figure 11. sdram write cycle 8.7 general purpose i/o timing table 33. gpio timing 1 notes: 1 gpio pins include: int, uart, and timer pins. num characteristic symbol min max unit g1 g2 clkout high to gpio output valid t chpov ?10ns clkout high to gpio output invalid t chpoi 1.5 ? ns g3 g4 gpio input valid to clkout high t pvch 9?ns clkout high to gpio input invalid t chpi 1.5 ? ns a[23:0] sd_sras sd_scas 1 d[31:0] actv pall nop ras [1:0] write row column sd_cke sd_we cas [3:0] d1 d2 d4 d8 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d2 d2 d4 d2
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 45 figure 12. gpio timing 8.8 reset and configurat ion override timing table 34. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 notes: 1 all ac timing is shown with respect to 50% v dd levels unless otherwise noted. num characteristic symbol min max unit r1 reset input valid to clkout high t rvch 9?ns r2 clkout high to reset input invalid t chri 1.5 ? ns r3 reset input valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rstout valid t chrov ?10ns r5 rstout valid to config. overrides valid t rovcv 0?ns r6 configuration override setup time to rstout invalid t cos 20 ? t cyc r7 configuration override hold time after rstout invalid t coh 0?ns r8 rstout invalid to configuration override high impedance t roicz ?1t cyc g1 clkout gpio outputs g2 g3 g4 gpio inputs
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 46 figure 13. reset and configuration override timing * refer to the coldfire integration m odule (cim) section for more information. 8.9 i 2 c input/output timing specifications table 35 lists specifications for the i 2 c input timing parameters shown in figure 14 . table 36 lists specifications for the i 2 c output timing parameters shown in figure 14 . table 35. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 start condition hold time 2 ? t cyc i2 clock low period 8 ? t cyc i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 ? t cyc i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? t cyc i9 stop condition setup time 2 ? t cyc table 36. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 1 start condition hold time 6 ? t cyc i2 1 clock low period 10 ? t cyc i3 2 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ?? s i4 1 data hold time 7 ? t cyc i5 3 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il =0.5 v) ?3 ns i6 1 clock high time 10 ? t cyc r1 r2 clkout reset rstout r3 r4 r8 r7 r6 r5 configuration overrides*: r4 (rcon , override pins])
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 47 figure 14 shows timing for the values in table 35 and table 36 . figure 14. i 2 c input/output timings 8.10 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. 8.10.1 mii receive signal timing (erxd[3:0], erxdv, erxer, and erxclk) the receiver functions correctly up to a erxclk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the pr ocessor clock frequency must exceed twice the erxclk frequency. table 37 lists mii receive channel timings. i7 1 data setup time 2 ? t cyc i8 1 start condition setup time (for repeated start condition only) 20 ? t cyc i9 1 stop condition setup time 10 ? t cyc notes: 1 note: output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta bl e 3 6 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2c_scl low period. the actual position is affected by the prescale and division val ues programmed into the ifdr; however, the numbers given in ta b l e 3 6 are minimum values. 2 because i2c_scl and i2c_sda are open-collect or-type outputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 specified at a nominal 50-pf load. table 36. i 2 c output timing specifications between i2c_scl and i2c_sda (continued) num characteristic min max units i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 48 figure 15 shows mii receive sign al timings listed in table 37 . figure 15. mii receive signal timing diagram 8.10.2 mii transmit signal timing (etxd[3:0], etxen, etxer, etxclk) table 38 lists mii transmit channel timings. the transmitter functions correctly up to a etxc lk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the pr ocessor clock frequency must exceed twice the etxclk frequency. the transmit outputs (etxd[3:0], etxen, etxer) can be programmed to transition from either the rising or falling edge of etxclk, and the timing is th e same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for detail s of this option and how to enable it. table 37. mii receive signal timing num characteristic min max unit m1 erxd[3:0], erxdv, erxer to erxclk setup 5 ? ns m2 erxclk to erxd[3:0], erxdv, erxer hold 5 ? ns m3 erxclk pulse width high 35% 65% erxclk period m4 erxclk pulse width low 35% 65% erxclk period table 38. mii transmit signal timing num characteristic min max unit m5 etxclk to etxd[3:0], etxen, etxer invalid 5 ? ns m6 etxclk to etxd[3:0], etxen, etxer valid ? 25 ns m7 etxclk pulse width high 35% 65% etxclk period m8 etxclk pulse width low 35% 65% etxclk period m1 m2 erxclk (input) erxd[3:0] (inputs) erxdv erxer m3 m4
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 49 figure 16 shows mii transmit si gnal timings listed in table 38 . figure 16. mii transmit signal timing diagram 8.10.3 mii async inputs signal timing (ecrs and ecol) table 39 lists mii asynchronous inputs signal timing. figure 17 shows mii asynchronous i nput timings listed in table 39 . figure 17. mii async inputs timing diagram 8.10.4 mii serial management channel timing (emdio and emdc) table 40 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. table 39. mii async inputs signal timing num characteristic min max unit m9 ecrs, ecol minimum pulse width 1.5 ? etxclk period table 40. mii serial management channel timing num characteristic min max unit m10 emdc falling edge to emdio output invalid (minimum propagation delay) 0? ns m11 emdc falling edge to emdio output valid (max prop delay) ? 25 ns m12 emdio (input) to emdc rising edge setup 10 ? ns m13 emdio (input) to emdc rising edge hold 0 ? ns m14 emdc pulse width high 40% 60% mdc period m15 emdc pulse width low 40% 60% mdc period m6 etxclk (input) etxd[3:0] (outputs) etxen etxer m5 m7 m8 ecrs, ecol m9
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 50 figure 18 shows mii serial management channel timings listed in table 40 . figure 18. mii serial management channel timing diagram 8.11 32-bit timer module ac timing specifications table 41 lists timer module ac timings. 8.12 qspi electrical specifications table 42 lists qspi timings. table 41. timer module ac timing specifications name characteristic 0?66 mhz unit min max t1 dt0in / dt1in / dt2in / dt3in cycle time 3 ? t cyc t2 dt0in / dt1in / dt2in / dt3in pulse width 1 ? t cyc table 42. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[1:0] to qspi_clk 1 510 tcyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid. (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns m11 emdc (output) emdio (output) m12 m13 emdio (input) m10 m14 m15
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 51 the values in table 42 correspond to figure 19 . figure 19. qspi timing 8.13 jtag and boundary scan timing table 43. jtag and boundary scan timing num characteristics 1 notes: 1 jtag_en is expected to be a static signal. henc e, specific timing is not associated with it. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4- t cyc j3 tclk clock pulse width t jcw 26 - ns j4 tclk rise and fall times t jcrf 03 ns j5 boundary scan input data setup time to tclk rise t bsdst 4- ns j6 boundary scan input data hold time after tclk rise t bsdht 26 - ns j7 tclk low to boundary scan output data valid t bsdv 033 ns j8 tclk low to boundary scan output high z t bsdz 033 ns j9 tms, tdi input data setup time to tclk rise t tapbst 4- ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 - ns j11 tclk low to tdo data valid t tdodv 026 ns j12 tclk low to tdo high z t tdodz 08 ns j13 trst assert time t trstat 100 - ns j14 trst setup time (negation) to tclk high t trstst 10 - ns qspi_cs[1:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 52 figure 20. test clock input timing figure 21. boundary scan (jtag) timing tclk v il v ih j3 j3 j4 j4 j2 (input) input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7
preliminary electrica l characteristics mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 53 figure 22. test access port timing figure 23. trst timing 8.14 debug ac timing specifications table 44 lists specifications for the de bug ac timing parameters shown in figure 25 . table 44. debug ac timing specification num characteristic 150 mhz units min max de0 pstclk cycle time 0.5 t cyc de1 pst valid to pstclk high 4 ns de2 pstclk high to pst invalid 1.5 ns de3 dsclk cycle time 5 t cyc de4 dsi valid to dsclk high 1 t cyc input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j14 j13
mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 preliminary electrical characteristics freescale semiconductor 54 figure 24 shows real-time trace timing for the values in table 44 . figure 24. real-time trace ac timing figure 25 shows bdm serial port ac timing for the values in table 44 . figure 25. bdm serial port ac timing de5 1 dsclk high to dso invalid 4 t cyc de6 bkpt input data setup time to clkout rise 4ns de7 clkout high to bkpt high z 0 10 ns notes: 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. table 44. debug ac timing specification (continued) num characteristic 150 mhz units min max pstclk pst[3:0] de2 de1 ddata[3:0] de0 dsi dso current next clkout past current dsclk de3 de4 de5 bkpt de6 de7
documentation mcf5271 integrated microprocessor ha rdware specification, rev. 1.2 freescale semiconductor 55 9 documentation table 45 lists the documents that provi de a complete description of the mcf5271 and their development support tools. documentation is av ailable from a local fr eescale distributor, a freescale semiconductor sales office, the freescale literatu re distribution ce nter, or through the freescal e world-wide web address at http://www.freescale.com . 9.1 document revision history table 46 provides a revision history for this document. table 45. mcf5271 documentation freescale document number title revision status mcf5271ec mcf5271 risc microprocessor hardware specifications rev. 1.2 this document mcf5271rm mcf5271 reference manual 1.1 available mcf5271pb mcf5271 product brief 0 available mcf5271fs mcf5271 fact sheet ? in process cfprodfact/d the coldfire fami ly of 32-bit microprocessors family overview and technology roadmap 0 available under nda mcf5xxxwp mcf5xxxwp white paper: motorola coldfire vl risc processors 0 available under nda mapbgapp mapbga 4-layer example 0 available cfprm/d coldfire family programmer's reference manual 2 available table 46. document revision history rev. no. substantive change(s) 0 initial release 1 - fixed several clock values. - updated signal list table 1.1 - removed duplicate information in the module de scription sections. the information is all in the signals description table. 1.2 - removed detailed signal description section. this information can be found in the mcf5235rm chapter 2. - removed detailed feature list. this inform ation can be found in the mcf5235rm chapter 1. - changed instances of motorola to freescale - added values for ?maximum operating junction temperature? in ta bl e 2 7 . - added typical values for ?core operating supply current (master mode)? in ta b l e 2 8 . - added typical values for ?pad operating supply current (master mode)? in ta b l e 2 8 . - removed unnecessary pll specifications, #6-9, in ta bl e 2 9 .
mcf5271ec rev. 1.2, 12/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or s pecifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004.

▲Up To Search▲

Price & Availability of PCF5271

	To Download PCF5271 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .